Levelized compiled code multi-delay logic simulation

Levelized Compiled Code (LCC) multi-delay simulation is an idea whose time has come. Although it is not a new idea, when it was first proposed the hardware and software technology of the time was not capable of meeting the demands of such a simulation technique[1]. The basic technique is to predict the points in time when each gate can change value, and generate simulation code to compute the output of the gate at those times. For multi-delay simulation in which each gate has an integer delay greater than or equal to one, many circuits require several megabytes of straight-line code. Running such code was technologically infeasible when the technique was first proposed. However, technology has caught up with the algorithm, and it is now possible to determine whether oblivious multi-delay simulation is a viable method of logic simulation. Our experimental data shows that oblivious multi-delay simulation is many times faster than eventdriven simulation for typical circuits, and significantly faster even with extremely demanding simulation parameters. Author